Technical Background and Career Objectives

I am looking for an R&D or post-doc position to work on challenges in next-generation technologies featuring advanced computing and algorithmic development. My technical background in diverse fields (algorithms, computer engineering, quantum computing, and parallel computation) has allowed me to identify and demonstrate new, unexpected synergies between circuit reliability, multicore computing, verification, and synthesis applications. Results of this cross-disciplinary research have been published at competitive conferences (ICCAD, DATE, HPCA, ASP-DAC). Finally, my interests are not limited to my past work, and I would also enjoy learning about other upcoming challenges in emerging technologies.

Education

Ph.D. in Comp. Science and Eng, University of Michigan Ann Arbor

MSE Comp. Science and Eng, University of Michigan (GPA: 8.0)

B.S.E. Comp. Eng, University of Michigan (GPA: 3.9–Summa Cum Laude)

May 2008

May 2004

May 2003

Work Experience

· Bioinformatics Specilist: Joward Hughes Medical Institute, Janelia Farm
April 2009 - Current

· Senior Engineer II: Synopsys Implementation Group 2008-March 2009

o Physical design innovation in leading industrial tool

o Logic synthesis innovation: patent pending

· Senior Engineer II: Synopsys Advanced Technology Group (ATG) 2008

o Research lab exploring advanced EDA solutions

· Teaching (graduate student instructor) 2006-2008

o EECS 381: Object-oriented programming (3 semesters)

o EECS 478: Logic Synthesis (2 semesters)

Research

Logic and Physical Synthesis

As physical characteristics become a more dominant factor in determining circuit performance, achieving design closure requires logic optimizations that can utilize accurate physical information available late in the design flow. We introduce a post-placement logic resynthesis strategy that exploits logic flexibility through simulation-based approximations. In particular, we guide efficient local optimizations with flexible objectives using global information.

Publications and software

· Synopsys: Patent Pending, 2009.

· "Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring," S. Plaza, I. Markov, and V. Bertacco, to appear in TCAD, 2009.

· "Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring," S. Plaza, I. Markov, and V. Bertacco, pp. 95-102, ISPD, 2008.
(Won Best Paper Award)

· "Node Mergers in the Presence of Don't Cares," S. Plaza, K-H. Chang, I. Markov, and V. Bertacco, pp. 414-419, ASP-DAC, 2007.

· "Boolean Operations on Decomposed Functions," S. Plaza and V. Bertacco, pp. 310-317, IWLS, 2005.

· "STACCATO: Disjoint Support Decompositions from BDDs through Symbolic Kernels," S. Plaza and V. Bertacco, pp. 276-279, ASP-DAC, 2005.

· Public software (STACCATO): http://www.eecs.umich.edu/vips/staccato/

Verification and Test

The intractability of fully verifying large designs necessitates intelligent strategies for uncovering design bugs that elude engineer-specified test suites. We introduce verification coverage metrics which we use to guide constrained-random simulation. Our simulation strategy evenly stimulates a design to expose corner-case behavior.

Publication

"Random Stimulus Generation using Entropy and XOR Constraints,” S. Plaza, I. Markov, and V. Bertacco, pp. 664-669, DATE, 2008.

Analysis and Improvement of Circuit Reliability

As device density increases, circuits become more susceptible to transient and permanent faults. We improve the reliability of a circuit by introducing techniques for automatically adding minimal amounts of redundancy. In particular, we expose combinational gate-level redundancies in logic to improve transient and permanent fault resilience.

Publications and Software

· “Signature-based SER Analysis and Design of Logic Circuits”, S. Krishnaswamy, S. Plaza, I. Markov, and J. Hayes, TCAD, 2009.

· “Enhancing Design Robustness with Reliability-aware Resynthesis and Logic Simulation,” S. Krishnaswamy, S. Plaza, I. Markov, and J. Hayes, pp. 149-154, ICCAD, 2007.

· "AnSER: A Lightweight Reliability Evaluator for use in Logic Synthesis," S. Krishnaswamy, S. Plaza, I. Markov, and J. Hayes, pp. 171-173, IWLS, 2007.

· "Architecting a Reliable CMP Switch Architecture," K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky, Vol.4, No. 1, Article 2, ACM Transactions on Architecture and Code Optimization, March 2007.

· "BulletProof: A Defect Tolerant CMP Switch Architecture," K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky, pp. 5-16, HPCA, 2006.

· "Assessing SEU Vulnerability via Circuit-Level Timing Analysis," K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky, Workshop on Architectural Reliability, 2005.

· Public software (AnSER): to be part of OAGear (http://openedatools.si2.org/oagear/)

Algorithms for Distributed and Parallel EDA Tools

As the growing complexity of IC designs challenges the scalability of CAD tools, commercial EDA development must embrace multicore systems, which have recently reached dominance in the server, workstation and desktop segments. However, the efficiency of CAD tools often depends on the throughput in solving multiple instances of computationally-hard problems. We introduce a priority-based scheduler, along with intelligent parallelization strategies, to efficiently solve multiple SAT problem instances on multicore systems.

Publications

· "Low-latency SAT Solving on Multicore Processors with Priority Scheduling and XOR Partitioning," S. Plaza, I. Markov, and V. Bertacco, to appear in IWLS, 2008.

· "Advances and Insights into Parallel SAT Solving," S. Plaza, I. Kountanis, Z. Andraus, V. Bertacco, and T. Mudge, pp. 188-194, IWLS, 2005.

Background and Training

· EDA courses taken[1]: logic synthesis (EECS 478), verification (EECS 578), physical design (EECS 527), compilers and architecture (EECS 570, 573, 583), algorithms (EECS 586)

· Experience

o synthesis tools: DesignCompiler (Synopsys), ABC & SIS (Berkeley)

o placement tools: Capo (UCLA & Michigan)

o quantum algorithm simulation: QuIDDPro (High-performance Quantum Circuit Simulation)

o industry data models and databases: OpenAccess (Si2)

o industry EDA software: OAGear (2nd place IWLS 2007 programming contest)

· Software development using the binary decision package CUDD

· Software development using the SAT solvers MiniSAT and zChaff

· Grading: introduction to electronic circuits (EECS 215)

Activities

· Organized weekly reading group on synthesis, verification, and test at Michigan

· Service: reviewer for DAC, TCAD, TODAES; member of Eta Kappa Nu

· Personal: volunteer weekly at hospital; tutor at elementary schools; Red Cross, member of roller-hockey league

[1] All course numbers given refer to the University of Michigan course catalogue

Stephen Michael Plaza's Website

"When life hands you lemons, don't accept them, it's a trap!"

Technical Background and Career Objectives

Education

Research